Micromachining fabrication techniques are used in, for example, manufacturing microelectromechanical systems (MEMS), dynamic random access memory (DRAM) capacitors, through silicon vias (TSVs) for 3D packaging, and novel structures for the emerging Internet of Everything (IoE) free-form electronics. Conventional micromachining techniques include surface micromachining for structures that are a few microns deep and bulk micromachining for deeper structures. Bulk micromachining techniques have been used for making deep structures with high aspect ratio, fine features, and smooth sidewalls.
One bulk micromachining technique uses a hard mask material to withstand sustained deep reactive ion etching (DRIE) of patterns in a substrate. The hard mask material could be a metal, due to their inertness, or thin oxide layers. FIG. 1 is a cross-section showing conventional deep etching with a metal hard mask. A hard mask layer 104 is deposited on a substrate 102 and patterned. The pattern in the hard mask layer 104 is then transferred into the substrate 102. The obtainable depth of the pattern into the substrate is, in part, dependent upon the characteristics of the hard mask layer 104.
Another bulk micromachining technique involves the use of a soft mask layer. FIG. 2 is a cross-section showing conventional deep etching with a soft hard mask. A soft mask layer 204, such as a photoresist layer or one or more other organic materials or non-metallic materials, is deposited on the substrate 102 and patterned. The pattern of the soft mask layer 204 is then transferred into the substrate 102. Photoresist (PR) and other soft materials are generally not suitable masks for DRIE processes. One such soft mask layer 204 may include a bilayer of oxide and photoresist and used for 300 μm deep etches. For tens of microns deep etches, photoresist masks may be sufficient. However, deeper trenches, such as for stretchable electronics where etching goes through the entire thickness of a silicon wafer, requires a hard mask of, for example, a Titanium/Gold bilayer.
The use of hard masks in deep etches (e.g., 100's of microns) imposes some limitations, especially for the semiconductor industry. The first challenge is the choice of the hard mask material. The DRIE time is affected, in part, by the depth of the trenches and the lateral dimensions due to the micro loading effect. The micro loading effect causes etching rate dependence such that narrower trenches would need more time to reach desired depth than wider features. This is explained by the effect of feature dimensions on trench conductance. The feature conductance is a measure of how easily reaction by-products can be vented and reactant gases can be supplied for more etching. As the trench depth (and aspect ratio) increases, the collisions between the leaving and entering gases increase, resulting in a dropping of the etch rate. Micro-loading results due to drop in feature conductance and narrower features suffer more because of the relative difficulty inherent in a smaller outlet/inlet trench.
The hard mask needs to be selective to the extremely long DRIE process, such that the mask is not etched during the process and at the same time the hard mask needs to be easily removed after the deep etch is performed. For instance, nickel is one conventional hard mask that supports deep etching, but nickel is difficult to remove using dry etching techniques. Further, nickel, and other metals, can bond with other materials used during the semiconductor manufacturing process and alter their chemistry. For example, nickel forms NiSi with silicon substrates when exposed to high temperatures. Alternatively, gold can be used as a hard mask, but gold does not adhere well to silicon and requires an underlying titanium layer for adhesion. Titanium readily oxidizes in air and is also hard to remove using dry etching. Alternatively, aluminum can be easily etched using metal RIE in halide gases, but aluminum forms alloys with silicon at the interface. One alternative to dry etching is wet etching. But, wet etching involves immersing the whole wafer causing contamination and selectivity issues that would not be suitable for complementary metal-oxide-semiconductor (CMOS) process flows, especially at an advanced stage after the devices are fabricated.
Another issue with the use of hard masks is the deposition method, which is sputtering in most cases. The metal/silicon interface is degraded due to ion bombardment during the deposition or diffusion (if alternative deposition methods, such as atomic layer deposition, are used at elevated temperature). Finally, even dry etching of a hard mask involves plasma and DC power that can detrimentally affect the surface roughness of the silicon or underlying material interface, which is also undesirable for MEMS manufacturing. Thus, conventional manufacturing techniques for deep etching present many challenges when using either hard masks or soft masks.